FIG. 1 shows a schematic top view of a display motherboard in the prior art, and FIG. 2 shows a schematic diagram of a section structure of a cutting area of the display motherboard in the prior art. As shown in FIGS. 1 and 2, in a manufacturing process of display panels 2, the display panels 2 are generally obtained by cutting a display motherboard 1, wherein the display motherboard 1 includes a plurality of display panels 2 arranged in a matrix. Specifically, the display motherboard 1 includes: a first substrate and a second substrate which are arranged oppositely; and sealant 3 arranged between the first substrate and the second substrate and used for sealing and bonding of the first substrate and the second substrate, wherein the sealant 3 defines a plurality of display panels 2 arranged in a matrix on the display motherboard 1. For example, the first substrate may be an array substrate, and the second substrate may be a color filter substrate 6. In this case, the display motherboard 1 further includes a cutting area 4 formed on the array substrate and corresponding to the sealant 3. Generally, the projection of the cutting area 4 on the array substrate is positioned within the projection of the sealant 3 on the array substrate, so that separated display panels 2 can be obtained by cutting the display motherboard 1 along the cutting area 4.
However, in the prior art, a few functional layers (relative to the functional layers remained at a portion, corresponding to the display areas of the display panels 2, of the array substrate) are remained at a portion, corresponding to the cutting area 4, of the array substrate, for example, as shown in FIG. 2, only some insulating layers (e.g., a planarization layer 7 and a gate insulating layer 8) are remained at the portion, corresponding to the cutting area 4, of the array substrate, while a source-drain layer, a gate layer and the like are not remained, so the distance between the portions, corresponding to the cutting area 4, of the array substrate and the color filter substrate 6 is relatively long, with thick sealant 3 coated therebetween, and during cutting, the display motherboard 1 is difficult to cut smoothly, and the sealant 3 is easily adhered to the substrates on two sides. Meanwhile, the functional layers (e.g., the planarization layer 7) remained at the portion, corresponding to the cutting area 4, of the array substrate are planar, so when the display motherboard 1 is cut by a cutter in the cutting area, the stress generated when the cutter cuts the display motherboard 1 is relatively dispersive; meanwhile, when the planarization layer 7, the gate insulating layer 8 and the like are greatly deformed under the stress to buffer the stress generated by the cutter, so that the stress is relatively small and unfavorable for cutting, and the display motherboard 1 is difficult to cut with a relatively small cutting driving force.